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Ordering number:ENN3945A
CMOS IC
LC83010N, 83010NE
Audio Digital Signal Processor
Overview
The LC83010N, 83010NE is a single-chip digital signal processor (DSP). It is designed for use in the application fields such as a digital processing of audio signals. The LC83010N, 83010NE CMOS processor has various on-chip filtering circuits such as a graphic equalizer for reproduction of sound quality. It also has simulation circuit for reverberation (sound reflection and echo), so that sound field with surround and delay can be created. The LC83010N and LC83010NE are upgraded versions of the LC83010 and the LC83010E. The LC83010N and LC83010NE have a 64fs clock output that enables improved interfacing with external A/D converters. TEST5 has been renamed FS640/T5 and incorporates both the new clock output and the original test output. * Surround DRAM access signal : 16 accesses/CH Max. (within 1 fs) Up to 2 256K (64K x 4 bits) DRAMs or 1M (256K x 4 bits) DRAMs can be directly connected to this chip. * Uses external DRAMS with RAS access times of 120 ns or lower. * Serial input/output interface with a microcomputer. Synchronous 8-bit serial input : 1 [Mail box (16 bits x 8) function available] Synchronous 8-bit serial output : 1 * Interrupt function (Vectored interrupt with the INT pin) * Stack Nesting Levels : 4 * On-chip Interval Timer : 12 bits (timer clock = sampling frequency) * Cycle time : 108ns (sampling frequency = 48kHz) * Single 5V power supply. * Package : 64-pin DIPs (LC83010N). 80-pin QFPs (LC83010NE). Note) When soldering QFP devices, do not use the solder dip method. * Evaluation chip : LC83EV010N (PGA100) * Applications * Graphic Equalizer * Power calculation for spectrum analyzer display * Sound field creation (using external DRAMs) * 4 Speakers + REC output
Features
LSI functions * Dual Harvard Architecture: Enables simultaneous processing (multiply and addition) of stereo signals in a single instruction cycle. The LC83010N, LC83010NE processor has the following two independent units: * Multiplier : 24 bits x 16 bits (fixed-point decimal) * ALU : 32-bit arithmetic calculation, 24-bit arithmetic and logical operations. * ACCumulator (ACC) : 32 bits * Temporal Registers (TMP0 to TMP7) : 32-bit for each * Internal Memory Data RAM 128 x 24 bits Coefficient RAM 256 x 16 bits Constant ROM 256 x 24 bits * Program memory Capacity (RAM) : 320 x 32 bits * A variety of I/O interfaces. * Audio signal I/O : 1 channel for input (applicable to various formats) 3 channel for output (applicable to up to 4 types of data format)
Development Environment
* Software Tools * Assembler * Debugger with simulation * Hardware Tools * IBM PC-AT compatible machines or AX personal computers * In Circuit Emulator (ICE)
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1001TN (KT)/N251JN KI No.3945-1/18
LC83010N, 83010NE Package Dimensions
unit:mm 3071-DIP64S
[LC83010N]
64 33
unit:mm 3174-QIP80E
[LC83010NE]
23.2 20.0 0.8 64 65
1.0
1.6
0.8
0.35
41 40
0.15
19.05
16.8
17.2
0.25
14.0
0.8
1
57.2
32
3.2 5.0max
4.0
1.6
80 1 24
25
3.0max 0.8
0.95
0.48
1.78
1.01
0.51min
2.7
21.6
0.8
SANYO : DIP64S
SANYO : QIP80E
Block Diagram
No.3945-2/18
15.6
LC83010N, 83010NE
Pin Assignments (DIP64S)
Top view
(QIP80E)
No.3945-3/18
LC83010N, 83010NE
Pin Function
Pin Name VDD1, 2 VSS1, 2 ASI1 ASI2 BCK1 BCK2 LRCKI LRCKO ASO AOBCK AOWCK AOTDF1 AOTDF2 DFBCK DFWCK RAS CAS DREAD DWRT A0 to 8 D0 to 7 SI SICK SIRQ SIAK SRDY SO SOCK SORQ SOAK P0 to 5 OSC1 OSC2 FS384O INT RES SELC TEST 1 to 4 FS64O/T5 I/O I I I I I I/O I O O O O O O O O O O O O O I/O I I I O I O I I O I/O I O O I I I I O Functional Description +5V power supply pins (These pins should be connected to the positive power source.) GND power supply pins (These pins should be connected to the ground level.) Audio data serial input 1 Audio data serial input 2 Bit clock input pin for ASI1 data Bit clock input pin for ASI2 data (I/O selectable by CR) Input pin for L/R channel distinguish signal (H: L channel data ; L: R channel data) Input pin for L/R channel distinguish signal (H: L channel data ; L: R channel data) Audio data serial output Bit clock output pin for ASO data (for 32fs and 48fs) Word clock output pin for ASO data Serial output pin for audio data (for high presence 1) Serial output pin for audio data (for high presence 2) Bit clock output pin for AOTDF1 and AOTDF2 data (for 32fs and 48fs) Word clock output pin for AOTDF1 and AOTDF2 data Output pin for RAS signal to external DRAMs Output pin for CAS signal to external DRAMs Output pin for data read signal to external DRAMs Output pin for data write signal to external DRAMs Output pins for address signals to external DRAMs (64K x 4 bits: A0 to A7, 256K x 4 bits: A0 to A8) Input/output pins for data transfer with external DRAMs. In the single DRAM configuration mode, pins D0 to D3 are used. In the double DRAM configuration mode, pins D0 to D7 are used. Input pin for serial data from control microcomputer (8-bit serial data) Serial clock input pin for SI data Request signal input pin for serial data input Output pin for Acknowledge response to the input request signal from a microcomputer Input pin for a Ready signal from a controlling microcomputer indicating the end of a data transfer Output pin for serial data to a controlling microcomputer (8-bit serial data) Serial clock input pin for SO data Request signal input pin for serial data output Output pin for Acknowledge response to the output request signal from a microcomputer General-purpose Input/Output ports (with on-chip pull-up resistor) Pin for connection with a crystal oscillator or for clock input from an external source. (384fs) Pin for connection with a crystal oscillator ( should be left open in external clock input mode) 384fs output pin Interrupt request input pin (with on-chip pull-up resistor) Reset input pin (with on-chip pull-up resistor) L/R channel signal select input pin with on-chip pull-down resistor ; L: external (LRCKI), H: internal (internal divider output) Test signal input pins. Normally, these pins should be connected to the ground level. Test signal output pins. 64fs clock output/test output. FS64O/T5 funcitons as a test output in test mode and as a 64fs clock output for external A/D converters during normal operation.
Control pins
Microcomputer I/F
DRAM I/F
Audio I/F (Interface)
No.3945-4/18
LC83010N, 83010NE
Pin Configuration Types
Level specification Circuit type Pin Name
TTL level output
ASO, AOBCK AOWCK, LRCKO, AOTDF1, AOTDF2, DFWCK, A0 to A8, FS384O, RAS, CAS, DREAD, DWRT, FS64O/T5
CMOS medium level current output
SO, SOAK, SIAK
Schmitt input
SOCK, SI, SICK, SORQ, SIRQ, SRDY
L level Schmitt input
BCK1, ASI1, ASI2, LRCKI
Normal input
TEST1 to 4
Input with internal pull-up resistor
RES, INT
Input with internal pulldown resistor
SELC
TTL level output Low level Schmitt input
BCK2, D0 to D7
Pu MOS medium current output Normal input
P0 to P5
No.3945-5/18
LC83010N, 83010NE Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter Maximum supply voltage Symbol VDDmax V01 V02 Input voltage Peak output current VIN IOP1 IOP2 IOP3 IOA1 IOA2 IOA3 Average output current IOA4 IOA1 IOA2 IOA3 IOA4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Audio I/F, DRAM I/F Microcomputer I/F P0 to P5 Audio I/F: Per pin Audio I/F, DRAM I/F: Per pin Microcomputer I/F: Per pin P0 to P5: Per pin Audio I/F: Total Audio I/F, DRAM I/F: Total Microcomputer I/F: Total P0 to P5: Total
Ta=-30 to +70C
Conditions
Ratings - 0.3 to +7.0 Up to the voltage produced by oscillation - 0.3 to VDD +0.3 - 0.3 to VDD +0.3 - 2 to +4 - 2 to +10 - 0.5 to +10 - 2 to +4 - 2 to +4 - 2 to +10 - 0.5 to +10 - 11 to +45 - 4 to +15 4 to +15 - 3 to +30 600 - 30 to +70 - 40 to +125
Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mW
C C
Note
Output voltage
OSC2 output Pins except for the OSC2
1 2 3 4 5 2 3 4 5 2 3
* When soldering QFP devices, do not use the solder dip method. Allowable Operating Conditions at Ta = -30 to +70C, VDD = 4.75V to 5.25V, VSS = 0V, unless otherwise noted
Parameter Operating supply voltage Input high-level voltage Symbol V DD VIH1 VIH2 VIH3 Input low-level voltage VIL1 VIL2 VIL3 fOP (T CYC) fEXT fEXTH fEXTL fEXTR fEXTF fEXT OSC1, OSC2, See figure 2. Applies to the OSC1 pin. See figure 1. (OSC1: input, OSC2: open) Audio I/F, DRAM I/F P0 to P5, SELC, TEST1 to 4 RES, INT, Microcomputer I/F Audio I/F, DRAM I/F P0 to P5, SELC, TEST1 to 4 RES, INT, Microcomputer I/F Up to 1% crystla oscillation error is allowed. max: 48kHz x 384 x 1.01 12.17 (165) 12.17 20 Conditions Ratings min 4.75 2 .4 0.7VDD
0.75VDD
typ
max 5.25
Unit V V V V
Note
6 7 6 7
0.8 0.3VDD
0.25VDD
V V V MHz (ns) MHz ns
Operating frequency (Instruction cycle time)
External clock input conditions
18.62 (107)ns 18.62
Frequency Pulse width Rise time Fall time
Crystal oscillation
10
ns
Self-oscillation conditions
oscillation frequency
18.62
MHz
oscillation stablizing period
fEXTS
See figure 3.
ms
Audio data input conditions
Transfer bit clock cycle
tBCYC tBCW tS tH
325
ns
Transfer bit clock pulse width
100 Applies to the BCK1 and BCK2 pins. See figure 4. 75
ns
Data set up time
ns
Data hold time
75
ns
Continued on next page.
No.3945-6/18
LC83010N, 83010NE
Continued from preceding page.
Parameter
Serial I/O clock conditions
Symbol tSCYC tSCW t SS tSH tDS tDH
Conditions
Ratings m in 650 325 75 75 41 typ max
Unit ns ns ns ns ns
Note
Serial clock cycle Serial clock pulse width Data set up time Data hold time Data set up time
Applies to the microcomputer interface. See figure 5. (Applies to the SICK, SOCK and SI pins.)
DRAM input conditions
Data hold time
Applies to the data input from external DRAM. See figure 6. (Timings between RAS, CAS and D0 to D7)
8
0
ns
8
Electrical Characteristics at Ta = -30 to +70C, VDD = 4.75V to 5.25 V, VSS = 0V, unless otherwise noted
Parameter Input low-level current Input high-level current Output high-level voltage Output low-level voltage Input leakage current Output-off leakage current Input/output capacitance
Audio data output timing
Symbol IIL1 IIL2 IIH VOH1 VOH2 VOL1 VOL2 IOFF
Conditions RES, INT, VIN=VSS P0 to P5, VIN=VSS SELC, Input pin with pull-down resistor IOH=- 0.4mA IOH=- 50A IOH=2mA IOH=10mA VIN=VSS to VDD VO=VSS, VDD
Ratings min - 250 -1 250 4.0
VDD- 1.2
typ
max
Unit A mA A V V
Note
1 2, 3 1 2, 3
0 .4 1.5 - 10 - 40 +10 +40 10
V V A A pF ns
Output data hold time
tOH tOD
20 Applies to audio data output. See figure 7. 100
Output data delay
ns
Microcomputer I/F output delay
Output data delay
tSD
Applies to serial data output. See figure 8.
100
ns
RAS H pulse width
Access timings for external DRAM
RAS L pulse width CAS H pulse width CAS L pulse width RAS address set up time RAS address hold time CAS address set up time CAS address hold time DWRT pulse width CAS-before-WRITE set up time Data set up time Data hold time
t RP tRAS t CP tCAS tRS tRH tCS tCH tW tWC tSD t HD C1, C2 IDD OSC1, OSC2, See figure 2. VDD1, 2, 18.62MHz external clock Data output timing for external DRAM. See figure 9. (Note) DRAM which has RAS access time below 120ns should be used.
95 150 80 101 0 20 0 40 50 0 0 50 20 50 100
ns ns ns ns ns ns ns ns ns ns ns ns pF mA
8 8 8 8 8 8 8 8 8 8 8 8
Crystal oscillation Current drain
(Note 1) TTL level output pins: ASO, AOBCK, AOWCK, LRCKO, BCK2, AOTDF1, AOTDF2, DFBCK, DFWCK, D0 to D7, A0 to A8, FS384O, RAS, CAS, DREAD, DWRT and FS64O/T5 (Note 2) CMOS medium current outputs: SO, SOAK, and SIAK (Note 3) Pu MOS medium current outputs: P0 to P5 (Note 4) TTL level outputs (first group): ASO, AOBCK, AOWCK, LRCKO, A0 to A8, D0 to D7, FS384O and BCK2 (Note 5) TTL level outputs (second group): AOTDF1, AOTDF2, DFWCK, RAS, CAS, DREAD, DWRT, and DFBCK (Note 6) L level Schmitt inputs pin: BCK1, BCK2, ASI1, ASI2, LRCKI, and D0 to D7 (Note 7) Schmitt input pins: RES, INT, SOCK, SI, SICK, SORQ, SIRQ, and SRDY (Note 8) The maximum load capacitance of RAS, CAS, DREAD, DWRT, D0 to D7 and A0 to A8 is 50pF.
No.3945-7/18
LC83010N, 83010NE
No.3945-8/18
LC83010N, 83010NE
No.3945-9/18
LC83010N, 83010NE
Program Load to The LC83010N - Boot procedure Programs must be loaded (boot strap) into the LC83010N (D2SP) from an external control unit (microcomputer) because its internal program memory consists of RAMs. The capacity of the program memory is 320 words x 32 bits. The procedural flow to load a 320-word program into the D2SP from a controlling microcomputer is shown in Figure A1. (1) Reset the entire system (microcomputer and D2SP) or reset the D2SP from the controlling microcomputer. After the D2SP is reset, it then enters the Boot mode. (2) Transfer the program to the D2SP from the microcomputer. The program is transferred to the D2SP in 8-bit synchronous serial communication mode. The program data of 8 bits x 16 data (equal to 4 instructions) is transferred to the D2SP continuously from the microcomputer, and followed by the SRDY signal. The D2SP stores that program data of 4 instructions to the internal mail box. The program data is then moved to the program RAM at the moment when the SRDY signal reaches the D2SP. (3) The operations discussed in (2) are repeated 80 times until the program data transfer of 320 instructions from the microcomputer to the D2SP is complete. (4) The D2SP automatically starts the program execution when the program loading of 320 instructions is complete. The program is transferred to the D2SP from the microcomputer in that manner.
Figure A-1. Example Program Boot Flow (D2SP Microcomputer)
No.3945-10/18
LC83010N, 83010NE
Figure A-2 gives the outline of an example program Boot system.
Figure A-2. Outline of an Example Program Boot System Development Tool System - Program development flow Development tools are provided to help the user to easily develop application programs for the D2SP. These development tools are divided into two groups: software support tool group and hardware support tool group. The software support tool group consists of an assembler, debugger and simulator. The hardware support tool group is realized as an InCircuit Emulator (ICE). Figure A-3 shows the applications development flow for the D2SP system. (1) Write an application source program. (2) Check the source program for syntax errors with the assembler. If every syntax error is corrected, the assembler generates a HEX program file. (3) Check the HEX file for operational errors with the simulator. If the desired operations are not successful, start the debugger to find what caused logical errors. (4) If program operations are checked successfully, use the ICE to evaluate the audio signal output. First, evaluate sound signals only with the ICE. In this evaluation process, the delay memory and microcomputer of the ICE are used. Second, start the total evaluation on an application system. In this evaluation stage, the AD/DA converters, microcomputer, and delay memory on the user application system are used. Figure A-4 shows the entire program development tool system for the D2SP. The software tools such as the assembler, debugger, simulator can be run on an IBM PC-AT compatible machine or an AX personal computer. The ICE is also controlled by such a host personal computer.
Figure A-3. Applications Development Flow
No.3945-11/18
LC83010N, 83010NE
Figure A-4. Entire Support Tool System for Microprogram Development (1) Debugger The debugger is a software support tool designed to realize virtual D2SP functional circuits. In this virtually emulated D2SP environment, user application programs can be evaluated as if they were executed on the real chip. The debugger is used mainly for logics analysis and detailed data analysis. Major functions of the debugger are listed in the table below, with brief explanation for each. * Display and Edit instructions These instructions can be used to display the contents of memory and registers on a screen and to update them. * Memory Fill instruction This instruction is used to fill a specified memory address range with a desired value. * Move instruction This instruction is used to transfer the data in a specified memory address range to another range. * Memory Load and Save instructions These instructions are used to transfer data between memory and disk. The memory load instruction enables the data transfer from a disk file to memory while the memory save instruction allows the data transfer from memory to a disk file. * Assemble and Unassemble instructions The assemble instruction is used to convert mnemonics into machine codes. The unassemble instruction is used to convert memory data back to mnemonics. * Emulation instruction control instruction and Break point instruction These instructions are used to execute the D2SP program and trace its operations. The break point instruction is used to set a point where the program execution stops. Table Major debugger functions
No.3945-12/18
LC83010N, 83010NE
(2) Outline of the simulator functions The application programs can be tested in the following sequence: * Inputting digital audio signals to the D2SP chip, * Executing a program, * Converting the audio output into analog signals, and * Measuring the analog signals with an oscilloscope or frequency characteristics meter (or sweep meter). The simulator enables the above operations on a personal computer. Figure A-5 shows the signal waveform measurement. This simulator has the following three measurement functions: 1) Audio output waveforms (sine waves) with respect to audio input waveforms (sine waves) 2) Frequency characteristics of audio output (AOUT) 3) Impulse response characteristics of audio output
Figure A-5. Display of Various Waveforms
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Figure A-6. Display of Frequency Characteristics
Figure A-7. Impulse Response Waveforms (Limit Cycle Characteristic)
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LC83010N, 83010NE
(3) ICE outline The In-Circuit Emulator (ICE) provides an operating environment where the application program already checked by the simulation debugger is executed and then outputs audio signals. The ICE functions can be divided into two: One is the program evaluation by outputting audio signals only on the ICE. In this evaluation method, delay can be produced by the DRAM in the ICE system. The other is the final program evaluation by connecting a user application board to the ICE system. In this test method, the interfaces to the controlling microcomputer and other various peripheral ICs on the application board can be evaluated. Figure A-8 shows the ICE system configuration for the entire evaluation using a user application board.
Figure A-8. Final Evaluation System Configuration with an Application Board and ICE ICE functions * The ICE has debugging functions. * The ICE consists of unique hardware functions specifically designed as the ICE for audio DSP. (a) ICE debugging functions (1) Execution command : Allows the program execution to continue until a break point is detected. It also enables the program execution in the step mode or in the trace mode. (2) Break function : Enables the user to set a desired break point. (3) The edit dump command is useful in displaying the conditions of a specified memory area after the break of program execution. The register edit command is used to convert the contents of a present specified register. (4) The memory dump command is useful in displaying the contents of a specified memory area when the program execution breaks. On the other hand, the edit command is used to edit the contents of a specified memory area when the program execution breaks. (5) Program modification and confirmation : Enables the user to modify part of the program and to check how it works. (6) Other functions : Memory management facility and so on. For details, refer the sections following section 8-3. (b) Unique ICE hardware configuration (1) Audio data input/output : Digital Interface Receiver (DIR). This function allows direct input of audio digital data. Digital Interface Transmitter (DIT). This function allows direct output of 3-channel digital audio data. (2) DRAM : Delay DRAM for audio signal. 256k (64k x 4 bits) x 2. 1M (256k x 4 bits) x 2 (3) Evaluation function of serial input/output : Z80 microcomputer for evaluating serial input/output. This control unit makes an access to the D2SP instead of any controlling microcomputer to adjust the serial input/output operations.
No.3945-15/18
LC83010N, 83010NE
Example Application System
No.3945-16/18
LC83010N, 83010NE
Instruction Bit Map The instruction bit map is shown below.
Instruction Bit Map Diagram
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LC83010N, 83010NE
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 2001. Specifications and information herein are subject to change without notice.
PS No.3945-18/18

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